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Why are FPGA’s less efficient than ASICs?

FPGA is ‘reconfigurable logic' device. Fabricate the chip first, design(reconfigure) it later.

ASIC is not meant for reconfiguration. You design first, give it to foundry, then chip is fabricated.

Now let's see how these chips are structured and what makes them different.

● Logic cell : Building block of FPGA

This is the smallest building block. The LUT acts as combinatorial logic. With help of DFF it forms sequential logic.

Let it be a Logic gate, mux, encoder, adder; any truth table can be stored in LUT as boolean expression.

One LUT can hold limited amount of data. And a logic cell has limited LUTs.

A boolean expression with many terms requires more memory space, the tool places the remaining terms into another logic cell. This requires routing of signals between them.

● FPGA signal routing :

The white line is a signal routed from one logic cell to another. You can imagine the wire length for greater logic implementation. This adds extra delays, reduces clock frequency, eats more area and power.

All of this just for capability of 'reconfuguarion'.

Even if the design doesn't need other cells or wires they are still present in FPGA chip consuming area and static power, making it less efficient.

● Standard cell : Building block of ASIC

A standard cell library can have a component as small as a NAND gate and IPs such as adder, FF, BRAM, mux etc.

All cells are well optimized for area and power.

● ASIC Layout :

Individual cells are closely connected to each other to form greater logic functions. Placement of cells is also optimized for signal propagation. In contrast to FPGA, ASIC doesn't have unnecessary logic and routing overhead. This consumes less area and power. Also achieves faster clocks.

Ultimately resulting into higher efficiency.