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What are free tools for HDL development for FPGA and ASIC?

Xilinx, Altera, Lattice Semiconductors, all FPGA vendors give away webpack versions of their FPGA design tools. These versions are limited to a certain set of devices and may have other limitations too.

However, they are all good enough for teaching. These vendors also donate licenses for free to academic institutions.

 

There are a few other open source synthesis flows which I will list below:

Qflow 1.0

Yosys Open SYnthesis Suite

Open source Verilog simulators which I have found to be good:

Icarus Verilog

Intro - Verilator - Veripool

Of course, one should not expect the same range of functionalities as in ModelSim or other commercial tools.

You can access Xilinx tools on-line without charge though the number of target devices is limited. For educational purposes The Xilinx WebPACK should be more than adequate and will support all contemporary languages (VHDL, Verilog, OpenCL) but does not support partial reconfiguration.

But if you are with an accredited institution with an established electronics engineering program pretty much all of the FPGA manufacturers and even the 3rd party tool providers offer free or extremely low cost access under their various university programs.